1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to an improvement in a row address signal generation circuit for a dynamic type semiconductor memory device.
2. Description of the Prior Art
FIG. 1 schematically shows the structure of a conventional dynamic type semiconductor memory device (DRAM) having 64 Kbit (65536 bit) memory cells.
Referring to FIG. 1, the conventional DRAM includes a memory cell array 1 for storing information.
The memory cell array 1 is formed by 65536 memory cells arrayed in the form of a matrix of rows and columns, a plurality of word lines for selecting a row of the memory cells and a plurality of bit lines for selecting a column of the memory cells. Each memory cell MC is formed by a capacitor C for storing information in the form of charges and a transfer gate Q for connecting the capacitor C to a bit line BL in response to a potential supplied to a word line WL. The transfer gate Q is formed by an insulated gate field effect transistor.
The conventional DRAM further has a clock generation part, an address decoder part and data input/output part as peripheral circuits of the memory cell array 1.
The clock generation part comprises an RAS clock generation circuit 17 for supplying a plurality of control signals of FET level (5 V) for controlling operations of various circuits relating to row addresses in response to an external clock signal RAS supplied to an input terminal 16 and CAS clock generation circuit 19 for generating a plurality of control signals of the FET level for controlling operations of various circuits relating to column addresses in response to a signal CAS supplied to an input terminal 18 and a control signal from the RAS clock generation circuit 17. The CAS clock generation circuit 19 is activated only when the signal RAS is in an activated state.
The address decoder part includes a row address part and a column address part. The row address part includes a row address buffer 5 which is activated in response to a control signal from the RAS clock generation circuit 17 to convert external address signals of TTL level (about 2.4 V) supplied to an address input terminal 6 into complementary 8-bit internal row address signals of the FET level, a row decoder 4 which is activated in response to a control signal from the RAS clock generation circuit 17 to decode the 8-bit internal address signals from the row address decoder 5 and select one from 256 (2.sup.8) combinations thereby to select a corresponding word line and a word driver circuit 3 which is activated in response to a control signal from the RAS clock generation circuit 17 to activate the selected word line in response to output from the row decoder 4. The word driver circuit 3 includes word line drivers provided in correspondence to respective word lines. The row decoder circuit 4 has unit row decoders provided in correspondence to the word lines, and outputs from the unit row decoders are supplied to corresponding word line drivers. Thus, a unit row decoder is selected by the internal row address signal from the row address buffer, so that a word line is selected and activated through a word line driver in the word driver circuit 3. Further, the address input terminal 6 is supplied with time-multiplexed external address signals, namely, the address input terminal 6 is first supplied with an external row address signal for selecting a row of the memory matrix and then with an external column address signal for selecting a column of the memory matrix. Such a DRAM for receiving time-multiplexed address signals is described in U.S. Pat. No. 3,969,706 entitled "Dynamic Random Access Memory MISFET Integrated Circuit".
The column address part comprises a column address buffer 9 which is activated in response to a control signal from the CAS clock generation circuit 19 to convert 8-bit external column address signals of the TTL level supplied through the address input terminal 6 into complementary 8-bit internal column address signals of the FET level and a column decoder circuit 8 which decodes the 8-bit internal column address signals from the column address buffer 9 and selects one from 256 (2.sup.8) combinations to select a corresponding bit line.
The data input/output part comprises a sense amplifier 2 which is activated in response to a control signal from the RAS clock generation circuit 17 to detect and amplify memory cell data read on each bit line, an I/O gate 7 which is activated in response to a control signal from the CAS clock generation circuit 19 to connect the bit line selected by the output of the column decoder 8 to a data input buffer 11 and a data output buffer 13, the data input buffer 11 which in response to a control signal from a R/W buffer receives input data D.sub.IN to be written through an input terminal 10 to convert the same into an internal data input signal of the FET level, the data output buffer 13 which in response to a control signal from the R/W buffer and a control signal from the CAS clock generation circuit 19 converts read data of the FET level supplied through the I/O gate 7 into an output signal of the TTL level to supply the same to an output terminal 12 and the R/W buffer 15 which in response to a control signal from the CAS clock generating circuit 19 converts an R/W signal of the TTL level for designating read/write operation mode supplied through an input terminal 14 into an internal R/W signal of the FET level. Output from the R/W buffer 15 is supplied to the data input buffer 11 and the data output buffer 13, to activate the data output buffer 13 in data reading and activate the data input buffer 11 in data writing.
Although FIG. 1 illustrates only one address input terminal 6, a plurality of such address input terminals 6 are provided to receive 8-bit address signals in a parallel manner.
Further, although the RAS clock generation circuit 17 illustrated in FIG. 1 generates only a single type of control signal, the respective circuits of the row address system are supplied with control signals which are different in timing from each other. Similarly the respective circuits of the column address system are supplied with control signals being different in timing from the CAS clock generation circuit 19.
It is generally believed that access time is the most important index of the performance of a semiconductor device. "Access time" is the time required for reading data from a memory cell after supply of an eternal address signal.
FIG. 2 is a waveform diagram showing data read operation of the DRAM as shown in FIG. 1. With reference to FIGS. 1 and 2, description is now made on the data read operation of the conventional DRAM.
As shown in FIG. 2, the operation is initiated by setting a row address signal for designating a row address corresponding to the address of a memory cell to be selected. Namely, external address signals A.sub.0 to A.sub.7 are supplied to the row address buffer 5 through the address input terminal 6. Then the signal RAS falls to a low level and the row address buffer 5 is responsively activated to generate an internal row address signal to supply the same to the row decoder 4. Then an external column address signal is supplied to the external address input terminal 6. Thereafter an external CAS signal falls to a low level, so that the external column address signal is strobed in the column address buffer 9. The column address buffer 9 is activated by a control signal from the CAS clock generation circuit 19 in response to the fall of the signal CAS to generate an internal column address signal and supply the same to the column decoder 8. Under control by the series of control signals from the RAS clock generation circuit 17 an the CAS clock generation circuit 19, the row decoder circuit 4, the word driver circuit 3, the sense amplifier 2, the column decoder 8 and the I/O gate 7 are activated so that information of the memory cell addressed by the external address signal is transmitted to the I/O gate 7. On the other hand, the R/W signal for designating the operation mode is set at, for example, a high level for designating read operation. This R/W signal is strobed in the R/W buffer 15 in response to the fall of he clock signal CAS, to be supplied to the data output buffer 13 and to the data input buffer 11. Thus, only the data output buffer 13 is activated in response to the CAS signal and the R/W signal so that read data from the I/O gate 7 is transmitted to the output terminal 12. Thus, the information is read from the selected memory cell.
Writing data into the memory cell is performed by setting the R/W signal at a low level. When the R/W signal is set at the low level, the data output buffer 13 enters a high impedance state while the data input buffer 11 is activated and data supplied to the data input terminal 10 is written into a memory cell selected through the I/O gate 7 at timing similar to that in reading.
Internal operation of the conventional DRAM as shown in FIG. 1 starts when the signal RAS enters an activated state, i.e., when the same falls to a low level, and hence the access time is defined by time t.sub.RAC (time from fall of the signal RAS to the low level to generation of the output data from the terminal 12) in FIG. 2.
FIG. 3 is a block diagram showing a circuit for generating a word line driving signal in the conventional DRAM. The word line driving signal is transmitted to a word line selected through the word driver circuit 3 as shown in FIG. 1. Referring to FIG. 3, a row decoder 4' for decoding internal row address signals of a predetermined combination applied from the row address buffer 5 and a dummy decoder 4a for defining a timing in generating a word line driving signal in response to a pair of row address signals RA.sub.n, RA.sub.n, and a word driver 3' for generating a word line driving signal to transfer the same onto a selected word line in response to the output of the row decoder 4' and the dummy decoder 4a are provided for one word line. Therefore, the row decoder circuit 4 as shown in FIG. 1 includes such row decoders 4' corresponding in number to the word lines and a dummy decoder 4'. The word driver 3' is provided for each word line.
Referring to FIG. 3, a conventional word line driving signal generation system comprises an RAS buffer 17a which generates a signal RAE for activating the row address buffer 5 in response to the external clock signal RAS supplied to the clock input terminal 16, a row address buffer 5 which is activated in response to the signal RAE to decode the 8-bit row address signals A.sub.0 to A.sub.7 supplied to the address input terminal 6 thereby to generate eight pairs of complementary internal row address signals RA.sub.n and RA.sub.n (n=0 to 7), row decoders 4' each of which is activated in response to a control signal from the RAS clock generation circuit 17 shown in FIG. 1 to decode 8-bit internal row address signals of a prescribed combination for outputting a high level signal RD in selection and outputting a low level signal RD in non-selection, the dummy decoder 4a for generating a signal RDD for providing rise timing of the potential of the selected word line in response to a predetermined pair of complementary internal address signals RA.sub.n and RA.sub.n from the row address buffer 5 and the word driver 3' for transmitting a word line driving signal WL to the selected word line in response to output from the row decoder 4' and that from the dummy decoder 4a.
The output line of the row decoder 4' is generally precharged at a high level, while output of the row decoder 4' connected to a selected word line remains at a high level and outputs of the row decoders 4' connected to non-selected word lines are discharged to low levels.
The dummy decoder 4a detects that either of the internal row address signals RA.sub.n or RA.sub.n is high, to output a clock signal RDD which goes high.
The word driver 3' is formed by an AND gate which receives the output of the row decoder 4' and that of the dummy decoder 4a. The rise timing of the signal RDD is set to be substantially simultaneous with the time when non-selected row decoder output RD falls to a low level. The reason for such timing is as follows. If the signal RDD rises before the low level of the signal RD is established, the word driver circuit 3' (two-input AND circuit) receiving the signals RD and RDD is not completely at a low level and a non-selected word line is selected in the so-called multiple choice manner, to cause malfunction of the memory device.
FIG. 4 is a waveform diagram showing the operation of the word line driving signal generation part as shown in FIG. 3. Referring to FIGS. 3 and 4, description is now made on the operation for generating the word line driving signal.
At a time t.sub.0, the row address signals A.sub.0 to A.sub.7 are applied to the address input terminal 6 to set the row address of the memory cell to be selected. Since the clock signal RAS is high at this time, the signal RAE remains low. Thus, the row address buffer 5 is not activated but merely receives the external row address signals A.sub.0 to A.sub.7, and all of its outputs are at low levels.
At a time t.sub.1 the clock signal RAS falls, so that the clock signal RAE from the RAS buffer 17a responsively rises to activate the row address buffer 5. The row address buffer 5 thus activated decodes the supplied external address signals A.sub.0 to A.sub.n to generate eight pairs of complementary internal row address signals RA.sub.n and RA.sub.n at a time t.sub.3 for supplying the 8-bit complementary row address signals RA.sub.n and RA.sub.n (n=0.about.7) of prescribed combinations to the row decoder 4' while supplying a predetermined pair of complementary row address signals RA.sub.n and RA.sub.n (n: one out of 0 to 7) to the dummy decoder 4a.
All of the outputs of the row address buffer 5 are at low levels before the time t.sub.3, and one of the pair of complementary internal address signals RA.sub.n and RA.sub.n goes high in response to the external address signals A.sub.0 to A.sub.7.
At a time t.sub.4, a selection/non-selection state of each row decoders 4' is established. Namely, the row decoder 4' decodes the 8-bit internal row address signals of prescribed combinations supplied from the row address buffer 5 to supply the high level signal RD when a corresponding word line is selected while outputting the low level signal RD if the corresponding word line is not selected. Since the output of the row decoder 4' is precharged at a high level before the time t.sub.3, the output signal line of the row decoder 4' connected to the non-selected word line is discharged to the low level.
On the other hand, the pair of complementary internal row address signals RA.sub.n and RA.sub.n from the row address buffer 5 are supplied to the dummy decoder 4a. The dummy decoder 4a detects rise of either the address signal RA.sub.n or RA.sub.n to a high level, to generate the clock signal RDD which goes high at a time t.sub.4.
At a time t.sub.5, the word line driving signal WL rises from the word driver 3' in response to the signals RD and RDD. Thus, the potential of the selected word line (word line designated by the row address) goes high. On the other hand, the output of the word driver 3' receiving the signals RD and RDD goes low since the signal RD is at a low level. Thus, the potential of the non-selected word line remains low.
Although the interval between the rising edges of the signal RDD and the word line driving signal WL, i.e., the interval between the times t.sub.4 and t.sub.5 is exaggerated in the waveform diagram of FIG. 4, the said signals rise substantially at the same time.
As hereinabove described, the conventional row address buffer does not operate from the falling edge of the clock signal RAS to the rising edge of the internal clock signal RAE.
FIG. 5 shows exemplary configuration of a conventional row address buffer.
Referring to FIG. 5, the conventional row address buffer comprises a circuit part 200 for receiving a clock signal RAE and generating an internal signal RAE and a circuit part 201 for converting an external address signal A.sub.n into an internal address signal A.sub.n response to the internal signal RAE from the circuit part 200.
The circuit part 200 is formed by an inverter which comprises a P-channel MOS transistor 129 and an N-channel MOS transistor, 130 complementarily connected with each other. The signal RAE supplied to an input terminal 131 is supplied to the gates of the MOS transistors 129 and 130. The signal RAE is outputted from a common node of a first conduction terminal of the PMOS transistor 129 and a second conduction terminal of the NMOS transistor 130. A second conduction terminal of the PMOS transistor 129 is connected to a supply poteial V.sub.CC. A first conduction terminal of the NMOS transistor 130 is connected to a ground potential.
The circuit part 201 comprises a P-channel MOS transistor 127 and an N-channel MOS transistor 128 which are complementarily turned on/off in response to the internal signal RAE and a P-channel MOS transistor 103 and an N-channel MOS transistor 104 which are complementarily turned on/off in response to an external address signal (one bit) supplied to an input terminal 102. The PMOS transistor 127 has a first conduction terminal connected to the supply potential V.sub.CC, a gate for receiving the signal RAE and a second conduction terminal connected to a first conduction terminal of the PMOS transistor 103. The PMOS transistor 103 has the first conduction terminal connected with the second conduction terminal of the PMOS transistor 127, a gate for receiving the internal signal RAE and a second conduction terminal connected to an output terminal 105. The NMOS transistor 128 is provided between the output terminal 105 and a ground potential, and receives the internal signal RAE in its gate. The NMOS transistor 104 is provided between the output terminal 105 and the ground potential in parallel with the NMOS transistor 128, and receives the external address signal in its gate through the input terminal 102.
Description is now made on the operation of the conventional row address buffer.
The signal RAE is inverted by the circuit part 200 to provide the signal RAE. Therefore, in a standby state in which the signal RAS is at a high level, the signal RAE is also high and the PMOS transistor 127 is in an OFF state while the NMOS transistor 128 is in an ON state. In such a state, the potential of the output terminal 105 is low with no regard to the address signal potential at the input terminal 102. When the signal RAE goes high and the signal RAE goes low in response to the fall of the RAS signal, the PMOS transistor 127 enters an ON state and the NMOS transistor 128 enters an OFF state so that the circuit part 201 functions as an inverter to output an inverted signal of the address signal supplied to the input terminal 102 from the output terminal 140. The PMOS transistor 127 is so provided that undesirable current can not flow between the supply potential V.sub.CC and the ground potential even if the potential of the address signal supplied to the input terminal 102 in the standby state (signal RAS is high) is 2.4 V of the TTL level.
The conventional semiconductor memory device is in the aforementioned structure, and the timing for strobing the row address signal has been provided by the external clock signal RAS. Since the access operation is started from setting of the row address as hereinabove described, the actual access time is t.sub.AAC in FIG. 2, i.e., the interval between the setting of the row address and outputting of the output data, which is longer by a time t.sub.ASR than the memory device access time t.sub.RAC, i.e., the interval between the trailing edge of the signal RAS and output of the output data. The time t.sub.ASR is a set-up time in which the row address signal must be established before the signal RAS goes low. This value is generally defined at 0 ns, whereas it is difficult to simultaneously supply all address signals in practice, and hence the set-up time is set with a margin of 10 ns to 20 ns. As the result, the access time t.sub.AAC is lengthened by the marginal time t.sub.ASR in actual operation.
A dynamic RAM for providing address signals in a time-divisional manner is described in U.S. Pat. No. 3,969,706 entitled "Dynamic Random Access Memory MISFET Integrated Circuit" by R. J. Proebsting et al. However, this prior art example shows no structure of zeronizing the address set-up time t.sub.ASR.
A semiconductor input circuit having small power consumption for an input signal of the TTL level is described in Japanese Patent Application No. 250247/1983 by the same inventor filed on Dec. 29, 1983 in the name of the same assignee of the present application. The semiconductor input of the reference circuit is intended to be applied to a buffer for converting a CS (chip select) signal of the TTL level into a CS signal of the FET level, but not to an address buffer.